Title :
Defect-tolerance design of the high-speed RSA encryption processor with built-in table for residue calculation of redundant binary numbers
Author :
Tomabechi, Nobuhiro ; Ito, Teruki
Author_Institution :
Hachinohe Inst. of Technol., Japan
fDate :
6/23/1905 12:00:00 AM
Abstract :
This paper presents a high-speed RSA encryption processor employing a highly parallel architecture based on the redundant binary number arithmetic and table-look-up, and also presents a defect-tolerance design suitable for the processor to solve the low yield problem. It is demonstrated that the gate delay through the critical path determining the operation speed of the processor is 1/60 that of the conventional processor. It is also demonstrated that the increase of chip size by introducing defect-tolerance is 6.4% and the increase of delay is minimized
Keywords :
computer architecture; cryptography; delays; digital signal processing chips; fault tolerant computing; high-speed integrated circuits; logic design; parallel architectures; redundancy; residue number systems; table lookup; chip size; critical path; defect-tolcrance design; defect-tolerance; gate delay; high-speed RSA encryption; low yield problem; operation speed; parallel architecture; redundant binary number arithmetic; table-look-up; Arithmetic; Computer networks; Computer security; Cryptography; Delay; Electronic mail; Hardware; Parallel architectures; Process design; Prototypes;
Conference_Titel :
Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on
Print_ISBN :
0-7803-7057-0
DOI :
10.1109/ICECS.2001.957731
