Title :
Bit-level architectures for Montgomery´s multiplication
Author :
Nibouche, O. ; Bouridane, A. ; Nibouche, M.
Author_Institution :
Sch. of Comput. Sci., Queen´´s Univ., Belfast, UK
fDate :
6/23/1905 12:00:00 AM
Abstract :
Algorithms and architectures for performing modular multiplication operations are important in cryptography and Residue Number System. In this paper Montgomery´s algorithm has been broken into two concurrent no-interleaved multiplication operations. The architectures derived from this algorithm are systolic and need near communication links only. Thus, very well suited for VLSI implementation. The presented architectures offer a great flexibility of finding the best trade-off between hardware cost and throughput rate by changing the digit size
Keywords :
VLSI; cryptography; digital signal processing chips; integrated circuit design; modules; multiplying circuits; parallel algorithms; residue number systems; systolic arrays; Montgomery´s algorithm; VLSI; concurrent no-interleaved multiplication; cryptography; digit size; hardware cost; modular multiplication; near communication links; residue number system; systolic architecture; throughput rate; Computer architecture; Computer science; Costs; Electronic commerce; Hardware; Public key cryptography; Safety; Security; Throughput; Very large scale integration;
Conference_Titel :
Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on
Print_ISBN :
0-7803-7057-0
DOI :
10.1109/ICECS.2001.957732
