Robustness Evaluation of MOSFETs by Equivalent Cell Behavioral Model of the Gate Parasitic Resistance

The main purpose of this work has been to carry out a complete analysis by simulation of the behavior of low- voltage power MOSFETs accounting for the effect of the gate parasitic-RC distribution. The use of a low-gate mesh resistance has been analyzed as an overall alternative to more traditional materials. Moreover, a design using mixed materials (poly-silicon material and low resistivity one) has been also investigated. The contribution of the gate metal resistivity has been accounted for with modeling and simulations. This study is devoted to the decrease of the switching speed, thus allows obtaining advantageous performances in terms of power losses. Moreover good results are shown that can be achieved in terms of robustness due to a more uniform switching within the device structure. The analysis has been realized building a complete model of the device for behavioral circuit simulators based on a preliminary discretization into elementary cells of the geometry. The results can be exploited to improve the device design especially from the point of view of a continuous scaling process. The increase of the switching speed allows managing both higher powers and operative frequency as it is required by new converters and more demanding applications. Seven different layouts are investigated.