Title :
Simultaneous shield and buffer insertion for crosstalk noise reduction in global routing
Author :
Zhang, Tianpei ; Sapatnekar, Sachin S.
Author_Institution :
Dept. of Electr. & Comput. Eng., Minnesota Univ., Minneapolis, MN, USA
Abstract :
We present a method for incorporating crosstalk reduction criteria into global routing under an innovative power supply architecture, while considering the constraints imposed by limited routing and buffering resources. An iterative procedure is employed to route the signal wires, assign supply shields, and insert buffers so that both buffer/routing capacity and signal integrity goals are met. In each iteration, shield assignment and buffer insertion are considered simultaneously via a dynamic programming-like approach. Our noise calculations are based on Devgan´s noise metric, and our work shows, for the first time, that this metric shows good fidelity on average. Experimental results on testcases with up to about 10,000 nets point towards an asymptotic run time that increases linearly with the number of nets. Our algorithm achieves noise reduction improvements of up to 53% and 28%, respectively, compared to methods considering only buffer insertion, or only shield insertion after buffer planning.
Keywords :
crosstalk; dynamic programming; iterative methods; noise; power engineering computing; power system protection; Devgan noise metric; buffer insertion; buffer planning; crosstalk noise reduction; crosstalk reduction criteria; dynamic programming; global routing; iterative procedure; power supply architecture; shield assignment; shield insertion; signal integrity; Circuit noise; Crosstalk; Delay effects; Integrated circuit interconnections; Noise level; Noise reduction; Power supplies; Routing; Switches; Wires;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings. IEEE International Conference on
Print_ISBN :
0-7695-2231-9
DOI :
10.1109/ICCD.2004.1347906