Title :
Delay models for verifying speed-dependent asynchronous circuits
Author_Institution :
Sch. of Comput. Sci., Carnegie Mellon Univ., Pittsburgh, PA, USA
Abstract :
It is demonstrated that the binary inertial delay model can lead to false positive results when used in the verification of speed-dependent asynchronous circuits. A delay model called the binary chaos delay model solves this problem in many cases. The two timing models are compared by using them in the verification of a FIFO controller circuit. The models can be viewed as two extremes of a more general, parameterized model
Keywords :
asynchronous sequential logic; delays; formal verification; logic circuits; FIFO controller circuit; binary chaos; binary inertial delay model; delay models; parameterized model; speed dependent asynchronous circuits verification; timing models; Asynchronous circuits; Chaos; Computer science; Continuous production; Delay effects; Design optimization; Formal verification; Hazards; Propagation delay; Timing;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1992. ICCD '92. Proceedings, IEEE 1992 International Conference on
Conference_Location :
Cambridge, MA
Print_ISBN :
0-8186-3110-4
DOI :
10.1109/ICCD.1992.276267
