Optimization of PWM dead times in DC/DC-converters considering varying operating conditions and component dependencies

PWM dead time related power losses degrade the converter efficiency, especially at low bus-voltages and high switching frequency. A reduction of these losses can be achieved by sensorless PWM dead time optimization approaches. In order to derive an optimization algorithm it is necessary to know the influence of dead times on the switching behavior and related power losses. This paper focuses on the reverse recovery charge for varying dead times and different MOSFET devices. Further experiments show, that there is an operating point dependency in optimal dead times. This is caused by a parasitic half-bridge capacitance. A behavioral model is derived from these experimental results. The model shows the quantitative influence of dead times on power losses. It is compared with measurements of the converter efficiency.