DocumentCode
1662666
Title
A two-step folder for a high-speed CMOS folding-and-interpolating ADC
Author
Han, Sang Chan ; Suh, Bum ; Kim, Soo Won
Author_Institution
Dept. of Electron. Eng., Korea Univ., Seoul, South Korea
Volume
1
fYear
2001
fDate
6/23/1905 12:00:00 AM
Firstpage
325
Abstract
Optimum design flow of a two-step folder for the input-bandwidth extension of a CMOS folding-and-interpolating ADC is presented. We derived the minimum transistor sizes of the two-step folder and analyzed the effects of the offset voltage. We implemented a folding-and-interpolating ADC adopting the two-step folder in a 0.25 μm 1P-5M CMOS process and got an experimental result of the input bandwidth of 50 MHz. This result verifies the design flow
Keywords
CMOS integrated circuits; analogue-digital conversion; high-speed integrated circuits; integrated circuit design; interpolation; 0.25 micron; 50 MHz; IP-5M process; high-speed CMOS folding-and-interpolating ADC; input bandwidth; offset voltage; optimum design flow; transistor size; two-step folder; Bandwidth; Bismuth; CMOS process; Design engineering; Equations; Frequency; Linearity; Signal design; Transfer functions; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on
Print_ISBN
0-7803-7057-0
Type
conf
DOI
10.1109/ICECS.2001.957745
Filename
957745
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