Synthesis of timed asynchronous circuits

A synthesis method that utilizes timing constraints to generate timed asynchronous circuits is presented. By unfolding the cyclic graph specification of an asynchronous circuit into an infinite acyclic graph, it is possible to use efficient algorithms to analyze the given timing constraints. A sufficient condition for the removal of redundancy in the specification is derived. Because of this condition, it is only necessary to analyze a finite subgraph of the infinite acyclic graph for derivation of a correct implementation. A systematic synthesis procedure that further optimizes the implementation based on the timing constraints is applied to the reduced specification. It is shown that the resulting timed implementation can be significantly reduced in complexity from its speed-independent counterpart while remaining hazard-free under the given timing constraints