Network-on-chip: the intelligence is in the wire

In this paper, we describe how network-on-chip (NoC) can be the next major challenge to implement complex and function-rich applications in advanced manufacturing processes at 90 nm technology and below. Although much progress has been made in connecting the various components encompassed in communication networks for system-on-chip (SoC) designs (e.g., processor-specific bus architectures, interface adapters, etc.), until now there has not been the possibility to consider a chip-wide architectural methodology that takes into account all typical NoC design requirements. As design complexity continues to increase, a more global approach is required to effectively transport and manage both on-chip and off-chip communication traffic, optimize wire efficiency and permit designs to scale in size, complexity, and IP block usage. The system described in this work is based on an innovative switching fabric that allows designers to build an efficient and scalable architecture for NoC implementation, without disrupting the existing IP interconnect solutions currently used in the design tools and flows.