DocumentCode
1662774
Title
Just in time scheduling
Author
Van Rompaey, Karl ; Bolsens, Ivo ; De Man, Hugo
Author_Institution
IMEC Lab., Leuven, Belgium
fYear
1992
Firstpage
295
Lastpage
300
Abstract
A just-in-time (JIT) scheduling approach that incorporates register optimizations during scheduling is introduced. The technique is implemented in a hierarchical list scheduler, SMART, that is part of the Cathedral silicon compiler. Due to its computational complexity it can schedule hierarchical graphs containing a thousand or more operations. Experiments on relevant industrial examples show a gain in registers of more than 25% due to the proposed register optimization
Keywords
VLSI; circuit layout CAD; scheduling; Cathedral silicon compiler; SMART; VLSI; computational complexity; hierarchical list scheduler; just-in-time scheduling; register optimization; register optimizations; Array signal processing; Digital signal processing; Hardware; Laboratories; Scheduling algorithm; Signal processing; Signal processing algorithms; Silicon; Time factors; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Design: VLSI in Computers and Processors, 1992. ICCD '92. Proceedings, IEEE 1992 International Conference on
Conference_Location
Cambridge, MA
Print_ISBN
0-8186-3110-4
Type
conf
DOI
10.1109/ICCD.1992.276273
Filename
276273
Link To Document