An optimised design of an improved voltage tripler

Author

Zhang, M. ; Llaser, N. ; Devos, F.

Author_Institution

Univ. de Paris-Sud, Orsay, France

Volume

1

fYear

2001

fDate

6/23/1905 12:00:00 AM

Firstpage

353

Abstract

An improved voltage tripler with a symmetrical stacking charge pump has been proposed. A pre-charge of parasitic capacitances has been added in this improved structure. Consequently the output voltage loss is reduced by a factor of 2. An optimised design of the improved voltage tripler for applications with a resistive load has been thus developed in terms of the circuit die area. The analysis shows that only with the optimised design the improved voltage tripler can offer the maximum output voltage of the theoretical limit, 3Vdd. A design example has been given

Keywords

CMOS analogue integrated circuits; circuit optimisation; integrated circuit design; voltage multipliers; 0.8 micron; 3 V; CMOS technology; circuit die area; dynamic analysis; optimised design; parasitic capacitances precharge; pump capacitors; resistive load; symmetrical stacking charge pump; symmetrical tripler; voltage tripler; Capacitors; Charge pumps; Clocks; Design optimization; EPROM; Equivalent circuits; Parasitic capacitance; Space vector pulse width modulation; Stacking; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on

Print_ISBN

0-7803-7057-0

Type

conf

DOI

10.1109/ICECS.2001.957752

Filename

957752