An efficient VLSI architecture for convolutional code decoding

In this paper, an efficient VLSI architecture for convolutional code decoding algorithm is presented. This algorithm locates all erroneous segments of the received sequence and then applies our proposed decoder to these segments only. Besides, the clock-gating technique is used to disable the non-working registers of our design to further reduce the power consumption efficiently with no bit error rate (BER) degradation. Experimental calculations indicate that our design yields more power reduction than the conventional Viterbi decoder.