Title :
Finite state machine decomposition using multiway partitioning
Author :
Yajnik, Maya K. ; Ciesielski, Maciej J.
Author_Institution :
Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
Abstract :
The problem of finite-state-machine decomposition into a number of smaller submachines is addressed. The number of submachines is decided by the algorithm on the basis of a partition of the outputs. The problem of determining the internal states in each submachine is formulated as a multiway partitioning of the original states using an m-way graph partitioning algorithm described herein. The results show an average of 39% decrease in delay and a small decrease in area for two-level implementations
Keywords :
delays; finite state machines; delay; internal states; m-way graph partitioning algorithm; multiway partitioning; two-level implementations; Added delay; Automata; Clocks; Control systems; Costs; Delay estimation; Flip-flops; Integrated circuit interconnections; Partitioning algorithms; Programmable logic arrays;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1992. ICCD '92. Proceedings, IEEE 1992 International Conference on
Conference_Location :
Cambridge, MA
Print_ISBN :
0-8186-3110-4
DOI :
10.1109/ICCD.1992.276280
