LUDMOS transistors optimization on a 0.18um SOI CMOS technology

Author

Toulon, G. ; Cortes, I. ; Morancho, F. ; Villard, B.

Author_Institution

LAAS, CNRS, Toulouse, France

fYear

2009

Firstpage

1

Lastpage

10

Abstract

This paper is focused on the design and optimization of power LDMOS transistors with the purpose of being integrated in a new generation of Smart Power technology based upon a 0.18 mum SOI-CMOS technology. Different LDMOS structures which allow breakdown voltages (V_BR) higher than 120 V have been analyzed by means of 2D and 3D TCAD simulations. The benefits of applying the shallow trench isolation (STI) concept along with the 3D RESURF concept in the LDMOS drift region is compared in terms of the main static (specific on-state resistance vs breakdown voltage (R_on-sp/V_BR) trade-off) and dynamic (Gate-to-Drain charge (Q_gd) and Gate charge (Q_g) vs R_on trade-off) characteristics. The influence of some drift region design parameters, such as the Poly-gate (L_Poly) and STI (L_STI) lengths, are also exhaustively analyzed in this work.

Keywords

CMOS integrated circuits; circuit optimisation; power MOSFET; silicon-on-insulator; 2D TCAD simulations; 3D RESURF concept; 3D TCAD simulations; SOI CMOS technology; Smart Power technology; lateral-double-diffused MOS transistor; power LDMOS transistors optimization; shallow trench isolation concept; size 0.18 mum; CMOS technology; Degradation; Indium phosphide; Isolation technology; MOSFET circuits; Power MOSFET; Power generation; Silicon on insulator technology; Uniform resource locators; Uninterruptible power systems; Power MOSFET transistor; RESURF; STI; Silicon-on-Insulator; Superjunction;

fLanguage

English

Publisher

ieee

Conference_Titel

Power Electronics and Applications, 2009. EPE '09. 13th European Conference on

Conference_Location

Barcelona

Print_ISBN

978-1-4244-4432-8

Electronic_ISBN

978-90-75815-13-9

Type

conf

Filename

5278827