A flexible data structure for efficient buffer insertion

With continuous down-scaling of minimum feature sizes and increasing of chip areas, buffering has become a necessary technique to control the interconnect delays in VLSI chips. Recently, Shi and Li proposed an efficient O(n log n) time algorithm to speed up buffering. Based on balanced binary search trees, their algorithm showed superb performance with the most unbalanced sizes of merging solution lists. We propose in this paper a more flexible data structure for the same buffering operations. With parameters to adjust, our algorithm works better than Shi and Li under all cases: unbalanced, balanced, and mix sizes. Our data structure is also simpler than theirs.