DocumentCode :
1662960
Title :
Simultaneous scheduling, binding and layer assignment for synthesis of vertically integrated 3D systems
Author :
Mukherjee, Madhubanti ; Vemuri, Ranga
Author_Institution :
Dept. of Electr. Comput. & Eng. Comput. Sci., Cincinnati Univ., OH, USA
fYear :
2004
Firstpage :
222
Lastpage :
227
Abstract :
Three-dimensional vertically integrated systems allow active devices to be placed on multiple device layers. In recent years, a number of research efforts have addressed physical synthesis issues for such systems. Such efforts showed a significant reduction in interconnect lengths. In order to effectively synthesize designs for 3D systems, it is necessary to take layer assignment for resources into consideration at higher levels of the design abstraction. We address the layer assignment problem as a part of a physical aware behavioral synthesis flow. We propose a 0-1 linear program formulation to perform simultaneous and optimal scheduling, binding and layer assignment for synthesizing designs for three-dimensional vertically integrated systems. The objective is to minimize inter-stratal via and the interconnect length in the critical path while taking thermal gradient between layers into account (which has been shown to be of particular concern for 3D systems). Floorplanning is performed for the synthesized design in order to estimate interconnect lengths. Results show a reduction of approximately 37% in total interconnect lengths on an average, compared to a traditional two-dimensional implementation when 2-5 layer implementations are examined.
Keywords :
circuit optimisation; data flow graphs; integer programming; integrated circuit interconnections; integrated circuit layout; linear programming; minimisation; 0-1 linear program; binding assignment problem; data flow graphs; floorplanning; interconnect length estimation; layer assignment problem; minimization; simultaneous scheduling; thermal gradient; three dimensional vertically integrated systems; vertically integrated 3D systems; Delay; Energy consumption; Fabrication; Integrated circuit interconnections; Moore´s Law; Optimal scheduling; Power system interconnection; Silicon; Stacking; Wafer bonding;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings. IEEE International Conference on
ISSN :
1063-6404
Print_ISBN :
0-7695-2231-9
Type :
conf
DOI :
10.1109/ICCD.2004.1347926
Filename :
1347926
Link To Document :
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