Title :
Implementation and bandwidth considerations in multi ported, on chip data cache
Author :
Besserglick, Asher ; Weiss, Shlomo
Author_Institution :
Dept. of Electr. Eng., Tel Aviv Univ., Israel
Abstract :
As CPU workload increases, the on-chip cache becomes a bottleneck for data transfer. In this paper, we evaluate the cache efficiency in terms of data bandwidth (BW), or the number of data accesses per cycle that a cache can handle. Four cache configurations are described and tested for the best BW performance. This paper deals not only with the type of two-level cache configuration but also with the best size ratios of the two levels. The results given are based on tests conducted with a cache simulation supporting two-level cache configurations
Keywords :
cache storage; performance evaluation; CPU workload; cache efficiency; cache simulation; data accesses; data bandwidth; data transfer; multi-ported on-chip data cache; performance; size ratios; two-level cache configurations; Bandwidth; Delay; Performance analysis; Pipelines; Read-write memory; System-on-a-chip; Testing;
Conference_Titel :
Electrical and Electronics Engineers in Israel, 1996., Nineteenth Convention of
Conference_Location :
Jerusalem
Print_ISBN :
0-7803-3330-6
DOI :
10.1109/EEIS.1996.566916
