Transistor and pin reordering for gate oxide leakage reduction in dual Tox circuits

Gate oxide tunneling current (I_gate) is emerging as a key roadblock for device scaling in nanometer-scale CMOS circuits. A practical means to reduce I_gate is to leverage dual T_ox processes where non-critical transistors are assigned a thicker T_ox. In this paper, we generate a leakage/delay tradeoff curve for dual T_ox circuits, and propose a transistor and pin reordering technique that has a minimal layout impact to further reduce the total leakage current up to 18% and I_gate up to 26% without incurring any delay penalty.