Title :
Transistor and pin reordering for gate oxide leakage reduction in dual Tox circuits
Author :
Sultania, Anup Kumar ; Sylvester, Dennis ; Sapatnekar, Sachin S.
Author_Institution :
Dept. of ECE, Minnesota Univ., Minneapolis, MN, USA
Abstract :
Gate oxide tunneling current (Igate) is emerging as a key roadblock for device scaling in nanometer-scale CMOS circuits. A practical means to reduce Igate is to leverage dual Tox processes where non-critical transistors are assigned a thicker Tox. In this paper, we generate a leakage/delay tradeoff curve for dual Tox circuits, and propose a transistor and pin reordering technique that has a minimal layout impact to further reduce the total leakage current up to 18% and Igate up to 26% without incurring any delay penalty.
Keywords :
CMOS digital integrated circuits; MOSFET; integrated circuit layout; leakage currents; logic gates; nanoelectronics; semiconductor device models; tunnelling; device scaling; dual Tox circuits; gate oxide leakage reduction; gate oxide tunneling current; integrated circuit layout; leakage current; leakage-delay tradeoff curve; nanometer scale CMOS circuits; pin reordering technique; transistor reordering technique; Circuits; Delay effects; Design optimization; Electrons; High K dielectric materials; Leakage current; MOSFETs; Nanoscale devices; Transistors; Tunneling;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings. IEEE International Conference on
Print_ISBN :
0-7695-2231-9
DOI :
10.1109/ICCD.2004.1347927
