High-throughput de-blocking filter accelerator for high-resolution H.264/AVC/SVC decoding

This paper presents a high-throughput deblocking filter accelerator which can process one macro block (MB) within 48 cycles for H.264/AVC/SVC. This innovation is achieved by considering both luminance and chrominance data together in arranging the filtering schedule. Cooperating with the filtering schedule, the proposed quadruple-filter-based architecture can simultaneously execute filtering of four edges. Besides, interleaved memory organization is adopted to eliminate all the data conflicts. This design keeps the input/output data order compliant with the raster scanning order so that no additional interfacing overhead is required for reordering the primary input and output data. After being implemented by using a 0.18-μm CMOS technology, this work can achieve the real-time performance requirement of 6K (6000 × 4000@30fps) format when operated at 135 MHz frequency at the cost of 41.6k gates along with 640 bytes single-port SRAM. Compared with previous works, the proposed design not only achieves higher real-time performance requirements but also possesses higher hardware computing efficiency.