A true logarithmic analog-to-digital pipeline converter with 1.5 bit/stage and digital correction

High-resolution pipeline analog-to-digital converters usually employ digital correction techniques to relax the requirements of the flash comparators, thus improving the performance of the converter. This paper exploits the same used common digital techniques to the class of non-linear ADCs, and in the special case of a true logarithmic pipeline converter. While the logarithmic operation is achieved by replacing the linear operations of subtraction and multiplication by simple scaling operations, the use of digital error correction allows to achieve high resolution and high dynamic range. An example is given to illustrate the proposed technique