Title :
On minimizing hardware overhead for pseudoexhaustive circuit testability
Author :
Kagaris, Dimitrios ; Makedon, Fillia ; Tragoudas, Spyros
Author_Institution :
Comput. Sci. Program, Dartmouth Coll., Hanover, NH, USA
Abstract :
A self-contained method with very low bypass storage cell (BSC) overhead is presented. The method uses a graph model to represent the circuit under test. This unifying model makes the method applicable to both the gate level and the module level. A non-necessarily-partitioning technique reduces the number of BSCs considerably
Keywords :
integrated circuit testing; large scale integration; logic testing; LSI; gate level; graph model; hardware overhead minimisation; logic testing; module level; nonnecessarily partitioning technique; pseudoexhaustive circuit testability; self-contained method; very low bypass storage cell; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Computer science; Feedback circuits; Flip-flops; Hardware; Linear feedback shift registers; Test pattern generators;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1992. ICCD '92. Proceedings, IEEE 1992 International Conference on
Conference_Location :
Cambridge, MA
Print_ISBN :
0-8186-3110-4
DOI :
10.1109/ICCD.1992.276289
