DocumentCode
1663194
Title
Delay/slope budgeting for clock buffer cell design
Author
Zhu, Qing K. ; Chan, Tim W.
Author_Institution
Intel Corp., Castro Valley, CA, USA
Volume
1
fYear
2001
fDate
6/23/1905 12:00:00 AM
Firstpage
417
Abstract
This paper presents a delay/slope budgeting method for clock buffers design in the standard cell library. The key idea is to include the skew estimation during the budgeting process. Within-die random variations such as the polyCD WL process, temperature and supply voltage are considered in the skew simulation for a 0.13 μm process
Keywords
CMOS digital integrated circuits; buffer circuits; clocks; delays; integrated circuit design; low-power electronics; timing circuits; 0.13 micron; buffer cell design; clock buffers; delay/slope budgeting method; microprocessor chips; polyCD WL process; skew estimation; standard cell library; supply voltage; temperature; within-die random variations; Capacitance; Clocks; Delay; Integrated circuit modeling; Libraries; MOSFETs; Microprocessors; Semiconductor device measurement; Temperature; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on
Print_ISBN
0-7803-7057-0
Type
conf
DOI
10.1109/ICECS.2001.957768
Filename
957768
Link To Document