Title :
Workload-driven floorplanning for MIPS optimization
Author :
Bose, Pradip ; LaPotin, David ; Vijayan, G. ; Kim, Sungho
Author_Institution :
IBM Thomas J. Watson, Res. Center, Yorktown Heights, NY, USA
Abstract :
An approach to early floorplanning in which optimization of a CPU chip floorplan is done in the context of a program benchmark (workload) is presented. The methodology integrates workload-driven cycles-per-instruction estimation into the traditional cycle-time evaluation process implied by an (early) floorplanning tool. This effectively adds an extra dimension to the floorplanning optimization cost function and search space, allowing superior MIPS-tuning of the VLSI chip
Keywords :
VLSI; circuit layout CAD; microprocessor chips; CPU chip floorplan; MIPS-tuning; VLSI chip; cycle-time evaluation process; cycles-per-instruction estimation; floorplanning optimization cost function; program benchmark; search space; workload-driven; Analytical models; CMOS logic circuits; Cost function; Design automation; Design optimization; High level synthesis; Logic design; Packaging; Routing; Very large scale integration;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1992. ICCD '92. Proceedings, IEEE 1992 International Conference on
Conference_Location :
Cambridge, MA
Print_ISBN :
0-8186-3110-4
DOI :
10.1109/ICCD.1992.276296
