• DocumentCode
    1663371
  • Title

    Analysis of asynchronous binary arbitration on digital-transmission-line buses

  • Author

    Kipnis, Shlomo

  • Author_Institution
    IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
  • fYear
    1992
  • Firstpage
    401
  • Lastpage
    406
  • Abstract
    The widely used asynchronous binary arbitration scheme on the digital-transmission-line model for buses is analyzed. A common misconception is that in this model, binary arbitration settles in at most four units of bus-propagation delay, regardless of the number of arbitration buses. This conjecture is disproved by showing that the settling time of binary arbitration depends on the arrangement of modules on the bus lines. An arrangement of modules on m buses for which binary arbitration settles only after m/2 units of bus-propagation delay is presented. It is also proved that for any arrangement of modules on m buses, binary arbitration settles in at most m/2+2 units of bus-propagation delay. It is then shown that for linear arrangements of modules in increasing order of priorities and equal spacings between modules, three units of bus-propagation delay are necessary and sufficient for binary arbitration to settle
  • Keywords
    delays; system buses; transmission line theory; asynchronous binary arbitration; bus lines; bus-propagation delay; digital-transmission-line buses; Computer science; Contracts; Degradation; Delay effects; Design engineering; Propagation delay; Signal analysis; Signal processing; System performance; Transmission lines;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer Design: VLSI in Computers and Processors, 1992. ICCD '92. Proceedings, IEEE 1992 International Conference on
  • Conference_Location
    Cambridge, MA
  • Print_ISBN
    0-8186-3110-4
  • Type

    conf

  • DOI
    10.1109/ICCD.1992.276301
  • Filename
    276301