Title :
A subthreshold SRAM cell with autonomous bitline-voltage clamping
Author :
Luo, Shien-Chun ; Chiou, Lih-Yih
Author_Institution :
Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
Abstract :
Ultra-low power SRAM is a promising memory for the next-generation electronics that focus on green and power-aware computing. Unfortunately, ultra-low power SRAM encounters serious timing uncertainty. One of the major problems is that the conventional voltage-clamping circuits cannot work when the bitlines have serious with-in-die variations. The full swing, usually required on the bitline, causes unwanted power dispassion. Therefore, this work proposes a novel SRAM cell that can clamp the bitline voltage autonomously. This voltage clamping is also independent in each bitline and is adapted automatically under dynamic voltage scaling. The dynamic power on bitline discharge can be saved by 75% by using the proposed structure, with an acceptable overhead in access time.
Keywords :
SRAM chips; clamps; low-power electronics; power aware computing; autonomous bitline-voltage clamping; next generation electronics; power aware computing; subthreshold SRAM cell; ultralow power SRAM; Discharges; Random access memory; Transistors; Wireless communication; Wireless sensor networks; SRAM; bitline; low power; subthreshold; voltage swing;
Conference_Titel :
Next-Generation Electronics (ISNE), 2010 International Symposium on
Conference_Location :
Kaohsiung
Print_ISBN :
978-1-4244-6693-1
DOI :
10.1109/ISNE.2010.5669177