Asymmetrical PWM Technique for a Three-Level Hybrid Inverter

Although the three-level neutral point clamped inverter is the most widely used multilevel topology, it still has some drawbacks mostly related to the balancing of the DC-link voltages across the capacitors and the unequal semiconductor stress. Many solutions devised in order to alleviate these problems rely on special symmetrical PWM modulation techniques which also increase the switching losses. This paper proposes an asymmetrical PWM modulation technique which is known to offer lower harmonic content as compared to the symmetrical modulation. The modulation technique is applied to a hybrid three-level inverter, which combines features from the traditional NPC and flying capacitors topologies. It is shown that the proposed technique is able to reduce the switching losses when compared to traditional the NPC and flying capacitor topologies. The paper also briefly shows how to extend the three-level topology to a general structure of N-levels. The proposed approach is implemented on a 16-bit fixed point DSP and tested on a three-phase 15 KVA IGBT-based PWM inverter.