The Message Driven Processor: an integrated multicomputer processing element

Author

Dally, William J. ; Chien, Andrew ; Fiske, J. A Stuart ; Fyler, Greg ; Horwat, Waldemar ; Keen, John S. ; Lethin, Richard A. ; Noakes, Michael ; Nuth, Peter R. ; Wills, D. Scott

Author_Institution

Artificial Intelligence Lab., MIT, Cambridge, MA, USA

fYear

1992

Firstpage

416

Lastpage

419

Abstract

A description is given of the Message-Driven Processor (MDP), an integrated multicomputer node. It incorporates a 36-bit integer processor, a memory management unit, a router for a 3D mesh network, a network interface, a 4K×36-bit word static RAM (SRAM), and an ECC dynamic RAM (DRAM) controller on a single 1.1 M-transistor VLSI chip. The MDP is not specialized for a single model of computation. Instead, it incorporates efficient primitive mechanisms for communication, synchronization, and naming. These mechanisms support most proposed parallel programming models. Each processing node of the MIT J-Machine consists of an MDP with 1 Mbit of DRAM

Keywords

VLSI; microprocessor chips; multiprocessing systems; parallel architectures; 1 Mbit; 1 Mbit DRAM; 144 Kbit SRAM; 144 kbit; 36 bit; 36-bit integer processor; 3D mesh network; DRAM; ECC dynamic RAM; MIT J-Machine; Message Driven Processor; Message-Driven Processor; SRAM; integrated multicomputer node; integrated multicomputer processing element; memory management unit; network interface; parallel programming models; static RAM; Communication system control; Computer network management; DRAM chips; Error correction codes; Memory management; Mesh networks; Network interfaces; Random access memory; Read-write memory; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Design: VLSI in Computers and Processors, 1992. ICCD '92. Proceedings, IEEE 1992 International Conference on

Conference_Location

Cambridge, MA

Print_ISBN

0-8186-3110-4

Type

conf

DOI

10.1109/ICCD.1992.276304

Filename

276304