• DocumentCode
    1663517
  • Title

    A minimal dual-core speculative multi-threading architecture

  • Author

    Srinivasan, Srikanth T. ; Akkary, Haitham ; Holman, Tom ; Lai, Konrad

  • Author_Institution
    Microarchit. Res. Lab., Intel Corp., USA
  • fYear
    2004
  • Firstpage
    360
  • Lastpage
    367
  • Abstract
    Speculative multi-threading (SpMT) can improve single-threaded application performance using the multiple thread contexts available in current processors. We propose a minimal SpMT model that uses only two thread contexts. The model achieves significant speedups for single-threaded applications using a low-overhead scheme for detecting and selectively recovering from data dependence violations, and a novel wrong path predictor to reduce the number of speculative threads executing along the wrong path. We also study the interactions between three previously proposed SpMT thread spawning policies that can be implemented dynamically in hardware - Fork on Call, Loop Continuation and Run Ahead policies - and show it is beneficial to implement all three policies together in a processor. While the individual thread spawning policies show performance benefits of 14%, 5% and 4% respectively on our SpMT model over a base processor that does not exploit SpMT, combining all three policies shows an average performance gain of 20%. Finally, we identify the sources of SpMT benefits - on average, 58% of the performance benefits due to SpMT comes from cache prefetching, 33% from instruction reuse, and 9% from branch precomputation and show all three sources of SpMT benefits must be utilized to realize the full potential of SpMT.
  • Keywords
    cache storage; multi-threading; multiprocessing systems; parallel architectures; branch precomputation; cache prefetching; data dependence violations; instruction reuse; minimal dual core architecture; multithreaded processors; single threaded applications; speculative multithreading architecture; thread spawning policy; wrong path predictor; Context modeling; Hardware; Microarchitecture; Multithreading; Performance gain; Performance loss; Predictive models; Prefetching; Registers; Yarn;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings. IEEE International Conference on
  • ISSN
    1063-6404
  • Print_ISBN
    0-7695-2231-9
  • Type

    conf

  • DOI
    10.1109/ICCD.2004.1347947
  • Filename
    1347947