Title :
An efficient VLSI architecture for HMM-based speech recognition
Author :
Jou, Jer Min ; Shiau, YeeHorng ; Huang, Chen-Jen
Author_Institution :
Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
fDate :
6/23/1905 12:00:00 AM
Abstract :
A high speed and area-efficient VLSI architecture for HMM-based speech recognition is presented in this paper. It is designed by optimally applying the special property in speech recognition known as the left to right state transition model (LRM) and utilizing look-ahead pipelining techniques to break the recurrence of the speech recognition operations. In order to verify the proposed architecture, we have also designed and implemented it in a hardware prototype with Xilinx FPGAs. The simulation and emulation results show the recognition speed can achieve 25,000 words per second under 92% recognition rate with 500 references and 10,000 test patterns by 10 speakers
Keywords :
VLSI; digital signal processing chips; dynamic programming; field programmable gate arrays; hidden Markov models; high-speed integrated circuits; parallel architectures; pipeline processing; speech recognition; speech recognition equipment; HMM-based speech recognition; Xilinx FPGAs; area-efficient VLSI architecture; complexity reduction; hardware prototyping; high speed VLSI architecture; isolated word speech recognition; left to right state transition model; look-ahead pipelining techniques; observation probability estimation; Emulation; Field programmable gate arrays; Hardware; Hidden Markov models; Pattern recognition; Pipeline processing; Prototypes; Speech recognition; Testing; Very large scale integration;
Conference_Titel :
Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on
Print_ISBN :
0-7803-7057-0
DOI :
10.1109/ICECS.2001.957780
