Title :
Modelling and simulation of design errors
Author :
Kang, Sungho ; Szygenda, Stephen A.
Author_Institution :
Comput. Eng. Res. Centre, Austin, TX, USA
Abstract :
When using simulation for design verification, only a subset of possible simulation patterns is used, since exhaustive simulation is usually not practical. When this subset is used, the designer wants to know how efficiently the design has been verified. The authors provide a measure of simulation pattern effectiveness, based on the concepts of design error modeling. This measure gives insight into the actual level of design validation that has been achieved. These concepts provide a basis for discussing a design validation metric
Keywords :
digital simulation; logic testing; design error modeling; design errors; design validation; design validation metric; design verification; simulation pattern effectiveness; simulation patterns; Analytical models; Circuits;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1992. ICCD '92. Proceedings, IEEE 1992 International Conference on
Conference_Location :
Cambridge, MA
Print_ISBN :
0-8186-3110-4
DOI :
10.1109/ICCD.1992.276310
