An architectural power estimator for analog-to-digital converters

This paper presents an architectural power estimation tool that can accurately estimate the power consumptions of analog-to-digital converters. Combining the advantages of both the bottom-up approach and the top-down approach, the estimator can help AMS SoC designer on high-level power optimized design without detailed knowledge of the circuit. The three-stage estimation process makes the estimator appropriate for architectural exploration of designs employing low power techniques. The framework makes it convenient to evaluate power dissipation of new customized architectures. Experimental results for 19 commercial designs show good estimation accuracy.