Design considerations for high resolution pipeline ADCs in digital CMOS technology

Author

Guilherme, Jorge ; Figueiredo, P. ; Azevedo, P. ; Minderico, G. ; Leal, A. ; Vital, J. ; Franca, José

Author_Institution

Integrated Circuits & Syst. Group, Instituto Superior Tecnico, Lisbon, Portugal

Volume

1

fYear

2001

fDate

6/23/1905 12:00:00 AM

Firstpage

497

Abstract

The trade-offs between bandwidth, resolution and power in high dynamic range pipeline analog-to-digital converters are studied when a pure digital CMOS technology is considered. Calibration techniques are presented to achieve the required resolution, and the design optimization methodology of the relevant pipeline building blocks are discussed. An example of a 15-bit 10 Ms/s analog-to-digital pipeline converter implemented in a 0.35 μm digital CMOS technology is presented

Keywords

CMOS integrated circuits; analogue-digital conversion; calibration; circuit optimisation; integrated circuit design; integrated circuit noise; pipeline processing; 0.35 micron; 15 bit; 2.7 to 3.3 V; 320 mW; analog-to-digital converters; bandwidth-resolution-power tradeoffs; calibration techniques; design optimization methodology; digital CMOS technology; high dynamic range ADC; high resolution ADCs; noise requirement; pipeline ADC; settling; Analog-digital conversion; Bandwidth; CMOS analog integrated circuits; CMOS digital integrated circuits; CMOS technology; Low-noise amplifiers; Noise reduction; Operational amplifiers; Pipelines; Quantization;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on

Print_ISBN

0-7803-7057-0

Type

conf

DOI

10.1109/ICECS.2001.957787

Filename

957787