Title :
A 19Gb/s serial link receiver with both 4-tap FFE and 5-tap DFE functions in 45nm SOI CMOS
Author :
Agrawal, Ankur ; Bulzacchelli, John ; Dickson, Timothy ; Liu, Yong ; Tierno, Jose ; Friedman, Daniel
Author_Institution :
IBM T. J. Watson Res. Center, Yorktown Heights, NY, USA
Abstract :
To overcome the limited bandwidth of chip-to-chip and backplane communication channels at multi-Gb/s data-rates, high-speed I/O transceivers employ a combination of DFE in the RX and FFE in the TX, since these equalizers complement each other to provide an effective equalization solution. Using RX-side FFE instead of TX-side FFE can bring important advantages to the transceiver: it obviates any back-channel for coefficient adaptation and improves RX interoperability with different TXs. RX-FFE is also preferable to simple peaking amplifiers, since it enables greater flexibility in setting the pre-cursor and post-cursor coefficients. However, traditional RX-FFEs with analog delay lines are not area efficient and do not support a wide range of data-rates. This paper describes design techniques that enable the realization of a RX with 4-tap FFE and 5-tap DFE, having area and power efficiency comparable to DFE-only RXs.
Keywords :
CMOS integrated circuits; decision feedback equalisers; radio transceivers; silicon-on-insulator; 4-tap FFE function; 5-tap DFE function; RX interoperability; RX-side FFE; SOI CMOS; analog delay lines; backplane communication channel; bit rate 19 Gbit/s; chip-to-chip communication channel; equalization solution; high-speed I/O transceiver; multi-Gb/s data-rate; power efficiency; serial link receiver; size 45 nm; CMOS integrated circuits; CMOS technology; Clocks; Decision feedback equalizers; Receivers; Semiconductor device measurement; Transceivers;
Conference_Titel :
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2012 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4673-0376-7
DOI :
10.1109/ISSCC.2012.6176951
