A 19Gb/s serial link receiver with both 4-tap FFE and 5-tap DFE functions in 45nm SOI CMOS

To overcome the limited bandwidth of chip-to-chip and backplane communication channels at multi-Gb/s data-rates, high-speed I/O transceivers employ a combination of DFE in the RX and FFE in the TX, since these equalizers complement each other to provide an effective equalization solution. Using RX-side FFE instead of TX-side FFE can bring important advantages to the transceiver: it obviates any back-channel for coefficient adaptation and improves RX interoperability with different TXs. RX-FFE is also preferable to simple peaking amplifiers, since it enables greater flexibility in setting the pre-cursor and post-cursor coefficients. However, traditional RX-FFEs with analog delay lines are not area efficient and do not support a wide range of data-rates. This paper describes design techniques that enable the realization of a RX with 4-tap FFE and 5-tap DFE, having area and power efficiency comparable to DFE-only RXs.