A new design of central queueing ATM switches

This paper introduces a new ATM switching architecture which integrates routing and buffering in the ATM switch. An output port oriented address management scheme is used in the proposed switching architecture, and all ATM cells are stored statically in the buffer. It is different from other common approaches which require cells to move through various sorting and routing stages inside the switch. The proposed switching architecture can easily support multicast/broadcast and priority scheduling. No cells will be duplicated in the buffer for multicasting/broadcasting. The proposed address management scheme lends itself readily to a straightforward VLSI implementation for the proposed ATM switch. Central queueing is used to achieve optimal throughput-delay performance and buffer utilization. This paper presents performance evaluation of the proposed ATM switching architecture in terms of throughput, queue size distribution, and central buffer occupancy distribution