High-performance sigma-delta ADC for ADSL applications in 0.35 μm CMOS digital technology

Author

Del Río, R. ; de la Rosa, J.M. ; Medeiro, F. ; Pérez-Verdu, B. ; Rodríguez-Vázquez, A.

Author_Institution

Instituto de Microelectron., CNM-CSIC, Seville, Spain

Volume

1

fYear

2001

fDate

6/23/1905 12:00:00 AM

Firstpage

501

Abstract

We present a sigma-delta modulator designed for ADSL applications in a 0.35 μm CMOS pure digital technology. It employs a 4th-order 3-stage cascade architecture including both single-bit and multi-bit quantizers with programmable resolution, which allows us to use an oversampling ratio of only 16 . Special emphasis is placed on technology issues, e.g. poor analog performance and substrate coupling. The measured performances are 13-bit dynamic range operating at 2 MS/s and 12-bit dynamic range operating at 4 MS/s. The modulator consumes 77 mW from a 3.3 V supply and occupies 1.32 mm²

Keywords

CMOS integrated circuits; cascade networks; digital subscriber lines; integrated circuit measurement; programmable circuits; quantisation (signal); sigma-delta modulation; signal resolution; signal sampling; telecommunication equipment; 0.35 micron; 3.3 V; 77 mW; ADSL applications; CMOS digital technology; analog performance; cascade architecture; dynamic range; measured performances; multi-bit quantizers; operating rate; oversampling ratio; power consumption; programmable resolution; sigma-delta ADC; single-bit quantizers; substrate coupling; CMOS technology; Capacitors; Circuits; Delta-sigma modulation; Digital modulation; Dynamic range; Performance evaluation; Quantization; Switches; Topology;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on

Print_ISBN

0-7803-7057-0

Type

conf

DOI

10.1109/ICECS.2001.957788

Filename

957788