DocumentCode :
1663803
Title :
Thermal-aware IP virtualization and placement for networks-on-chip architecture
Author :
Hung, W. ; Addo-Quaye, C. ; Theocharides, T. ; Xie, Y. ; Vijakrishnan, N. ; Irwin, M.J.
Author_Institution :
Embedded & Moblie Comput. Design Center, Pennsylvania State Univ., University Park, PA, USA
fYear :
2004
Firstpage :
430
Lastpage :
437
Abstract :
Networks-on-chip (NoC), a new SoC paradigm, has been proposed as a solution to mitigate complex on-chip interconnect problems. NoC architecture consists of a collection of IP cores or processing elements (PEs) interconnected by on-chip switching fabrics or routers. Hardware virtualization, which maps logic processing units onto PEs, affects the power consumption of each PE and the communications among PEs. The communication among PEs affects the overall performance and router power consumption, and it depends on the placement of PEs. Therefore, the temperature distribution profile of the chip depends on the IP core virtualization and placement. In this paper, we present an IP virtualization and placement algorithm for generic regular network on chip (NoC) architecture. The algorithm attempts to achieve a thermal balanced design while minimizing the communication cost via placement. Our framework can also realize hardware virtualization which can further accomplish better performance. A case study on low density parity checks (LDPC) decoder is presented to evaluate our algorithm.
Keywords :
genetic algorithms; integrated circuit design; integrated circuit interconnections; minimisation; parity check codes; switching networks; system-on-chip; telecommunication network routing; temperature distribution; LDPC decoder; SoC paradigm; communication cost minimisation; hardware virtualization; low density parity check decoder; networks-on-chip architecture; on-chip interconnect problems; on-chip switching fabrics; placement algorithm; processing elements; router power consumption; temperature distribution; thermal aware IP core virtualization; thermal balanced design; Algorithm design and analysis; Communication switching; Costs; Energy consumption; Fabrics; Logic; Network-on-a-chip; Parity check codes; Platform virtualization; Temperature distribution;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings. IEEE International Conference on
ISSN :
1063-6404
Print_ISBN :
0-7695-2231-9
Type :
conf
DOI :
10.1109/ICCD.2004.1347958
Filename :
1347958
Link To Document :
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