Library mapping of CMOS-switch-level-circuits by extraction of isomorphic subgraphs

The theoretical background required for a novel approach in the automatic layout generation for CMOS complex gates is described. This approach is directed at the automatic synthesis of complex gate structures using optimized substructures. The focus is on the efficient detection of subgraphs representing existing floorplans of subcells from larger graphs representing complex gates. The data structures and algorithms of the derived program are based on the mathematical description of CMOS switch-level circuits. The foundation of the graph model, called a multiplace graph, is presented in a novel and extended version