Digital background calibration for pipelined ADCs

Pipelined ADCs with more than 12 bits of resolution typically require linearity enhancement. This paper shows that the gain errors of both the sub DACs and interstage amplifiers in a pipelined ADC can be digitally corrected. A background calibration method is developed employing an energy free methodology for both single and multi stage errors and simulation results are presented to demonstrate the effectiveness of the proposed method.