Title :
Design of robust-path-delay-fault-testable combinational circuits by Boolean space expansion
Author :
Xie, X. ; Albicki, A. ; Krasniewski, A.
Author_Institution :
Dept. of Electr. Eng., Rochester Univ., NY, USA
Abstract :
A procedure for the design of robustly path-delay-fault testable two-level circuits by adding extra inputs to the circuits, using the method called Boolean space expansion is proposed. 100% path delay fault testable two-level circuits are achieved with area overhead in the range of 3% to 30%. A procedure to make the multilevel circuits fully testable is also reported. The results for several ISCAS benchmark circuits are presented
Keywords :
built-in self test; circuit CAD; delays; design for testability; Boolean space expansion; ISCAS benchmark circuits; robust-path-delay-fault-testable combinational circuits; Circuit faults; Circuit synthesis; Circuit testing; Combinational circuits; Delay effects; Electrical fault detection; Fault detection; Logic testing; Robustness; Very large scale integration;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1992. ICCD '92. Proceedings, IEEE 1992 International Conference on
Conference_Location :
Cambridge, MA
Print_ISBN :
0-8186-3110-4
DOI :
10.1109/ICCD.1992.276321
