Distributed VLSI simulation on a network of workstations

Author

Karthik, Sankaran ; Abraham, Jacob A.

Author_Institution

Comput. Eng. Res. Center, Texas Univ., Austin, TX, USA

fYear

1992

Firstpage

508

Lastpage

511

Abstract

Switch level simulation has been mapped to a distributed platform using a network of workstations. Model parallelism is used with preprocessing to partition the circuit to be simulated among the processors. A high-level pipelining scheme with multiple buffers is proposed to overcome the effects of a low-bandwidth network. Speedups of up to 4.1 with five processors have been obtained for medium sized ISCAS benchmark circuits. The speedups achieved using distributed simulation are very close to those obtained with the same switch-level simulator implemented on a shared-memory parallel machine

Keywords

VLSI; circuit CAD; digital simulation; distributed processing; pipeline processing; shared memory systems; ISCAS benchmark circuits; VLSI simulation; distributed platform; distributed simulation; high-level pipelining; low-bandwidth network; multiple buffers; shared-memory parallel machine; switch-level simulator; Bandwidth; Circuit simulation; Computational modeling; Distributed processing; Jacobian matrices; Parallel processing; Pipeline processing; Switches; Very large scale integration; Workstations;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Design: VLSI in Computers and Processors, 1992. ICCD '92. Proceedings, IEEE 1992 International Conference on

Conference_Location

Cambridge, MA

Print_ISBN

0-8186-3110-4

Type

conf

DOI

10.1109/ICCD.1992.276328

Filename

276328