Hierarchical simulation of MOS circuits using extracted functional models

A method for extracting functional models from the switch- (or gate-) level description of a circuit is presented. Model extraction is done incrementally while the hierarchical structure of the circuit is maintained. Extracted models are represented by Boolean functions that are compiled and linked to the simulator. A prototype simulator was implemented within the CHAMP framework. Simulations using extracted models executed 2.5 to 3 times faster than ordinary switch-level simulations without any loss of accuracy