Title :
Hierarchical simulation of MOS circuits using extracted functional models
Author :
Wehbeh, Jalal A. ; Saab, Daniel G.
Author_Institution :
Center for Reliable & High-Performance Comput., Illinois Univ., Urbana, IL, USA
Abstract :
A method for extracting functional models from the switch- (or gate-) level description of a circuit is presented. Model extraction is done incrementally while the hierarchical structure of the circuit is maintained. Extracted models are represented by Boolean functions that are compiled and linked to the simulator. A prototype simulator was implemented within the CHAMP framework. Simulations using extracted models executed 2.5 to 3 times faster than ordinary switch-level simulations without any loss of accuracy
Keywords :
Boolean functions; CMOS integrated circuits; digital simulation; logic CAD; Boolean functions; CHAMP framework; MOS circuits; extracted functional models; hierarchical simulation; hierarchical structure; switch-level simulations; Boolean functions; Circuit simulation; Computational modeling; Logic circuits; Logic devices; MOS devices; Maintenance; Signal design; Switches; Switching circuits;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1992. ICCD '92. Proceedings, IEEE 1992 International Conference on
Conference_Location :
Cambridge, MA
Print_ISBN :
0-8186-3110-4
DOI :
10.1109/ICCD.1992.276329
