DocumentCode
1664009
Title
Combined channel segmentation and buffer insertion for routability and performance improvement of field programmable analog arrays
Author
Huang, Hu ; Bernstein, Joseph B. ; Peckerar, Martin ; Luo, JI
Author_Institution
Dept. of ECE, Maryland Univ., College Park, MD, USA
fYear
2004
Firstpage
490
Lastpage
495
Abstract
In this paper, we propose a combined channel segmentation and buffer insertion approach, which minimizes the number of buffers inserted while satisfying the delay constraints for routing channels of field-programmable analog arrays. A segmented routing algorithm based on minimum-cost-bipartite-matching is improved with demand awareness and used to evaluate the various routing channels generated. Experiments show that, compared to a sequential segmenting-then-buffering design, our approach can significantly reduce the total number of buffers required, while achieving improved routability and minimum average interconnect delay. It is also shown that by increasing the number of long segment appropriately, the algorithm can dramatically improve the routability with a moderate increase on the number of buffers.
Keywords
buffer circuits; field programmable analogue arrays; bipartite matching; buffer insertion; channel segmentation; delay constraints; field programmable analog arrays; interconnect delay problem; routability problem; routing algorithm; routing channels; Analog circuits; Delay; Educational institutions; Field programmable analog arrays; Integrated circuit interconnections; Large-scale systems; Resource management; Routing; Switches; Wire;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings. IEEE International Conference on
ISSN
1063-6404
Print_ISBN
0-7695-2231-9
Type
conf
DOI
10.1109/ICCD.2004.1347966
Filename
1347966
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