Multi-FPGA implementation of a Network-on-Chip based many-core architecture with fast barrier synchronization mechanism

In this paper, we propose a fast barrier synchronization mechanism, targeting Network-on-Chip based many-core architectures. Its salient feature is that, once the barrier condition is reached, the “barrier release” acknowledgement is routed to all processor nodes in a broadcast way in order to save area by avoiding storing source node information and to minimize completion time by eliminating serialization of barrier releasing. Then, we construct a multi-FPGA platform using Xilinx^® Virtex 5 as FPGA chips and implement a NoC based many-core architecture on it. FPGA utilization and simulation results show that our mechanism demonstrates both area and performance advantages over the barrier synchronization counterpart with unicast barrier releasing.