DocumentCode
1664763
Title
A 464GOPS 620GOPS/W heterogeneous multi-core SoC for image-recognition applications
Author
Tanabe, Yasuki ; Sumiyoshi, Masato ; Nishiyama, Manabu ; Yamazaki, Itaru ; Fujii, Shinsuke ; Kimura, Katsuyuki ; Aoyama, Takuma ; Banno, Moriyasu ; Hayashi, Hiroo ; Miyamori, Takashi
Author_Institution
Toshiba, Kawasaki, Japan
fYear
2012
Firstpage
222
Lastpage
223
Abstract
The use of image recognition technologies is becoming more popular recently in a variety of industries such as automotive, surveillance, and others. SoCs for such image recognition applications are required to be powerful enough to support real-time multiple object recognition, with power consumption not exceeding a few Watts. Adaptability to a range of applications is also desirable. In this context, massively parallel processors and heterogeneous many-core processors with 200GOPS have been proposed. However, rising demands for simultaneous execution of multiple applications leads to even higher performance requirements. In advanced driver-assistance systems for automotive, for example, forward collision warning and traffic sign recognition should execute simultaneously to improve safety of the system. In addition, the accuracy of recognition is also important. With its high accuracy (96% detection rate/0.1% false-positive rate), object recognition using co-occurrence histograms of oriented gradients (CoHOG) is a promising algorithm. However, the algorithm requires an extensive amount of computation. For example, a desktop computer with a 3GHz quad-core processor is needed for CoHOG-based pedestrian detection in a backover prevention (BOP) application. Considering these requirements, we have developed an image recognition SoC with the following features: 1) a multi-core processor to provide adaptability to various applications; 2) accelerators for image processing tasks and image recognition tasks to realize high performance at low power consumption; and, 3) a hardware accelerator for a CoHOG based real-time recognition.
Keywords
digital signal processing chips; image recognition; multiprocessing systems; object recognition; system-on-chip; automotive; backover prevention application; cooccurrence histogram; desktop computer; driver assistance systems; forward collision warning; frequency 3 GHz; hardware accelerator; heterogeneous many-core processor; heterogeneous multicore SoC; image processing task; image recognition; multicore processor; object recognition; oriented gradient; parallel processor; pedestrian detection; quad-core processor; real-time recognition; surveillance; traffic sign recognition; Histograms; Image recognition; Multicore processing; Parallel processing; Power demand; Program processors; System-on-a-chip;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2012 IEEE International
Conference_Location
San Francisco, CA
ISSN
0193-6530
Print_ISBN
978-1-4673-0376-7
Type
conf
DOI
10.1109/ISSCC.2012.6176984
Filename
6176984
Link To Document