An analysis of designing 2D/3D chip multiprocessor wit different cache architecture

Network-on-Chip (NoC) has become a widely accepted on-chip communication architecture which provides a promising solution to integrate a large number of components on a single chip. However, with the increasingly higher performance demands for on-chip systems, NoCs are facing several critical challenges such as wire delay and power consumption. Therefore, in this paper, we explore different cache architecture designs in 2D/3D NoC architectures. Integrated core/cache and split and wire delay. We present benchmark results using a cycle accurate full system simulator. Experiments show that, by using the proposed 3D NoC architecture, compared with the integrated core/cache design, the average network latency and average link utilization are reduced by 5.01% and 26.07% respectively.