Targeting tiled architectures in design exploration

Tiled architectures can provide a model for early estimation of global interconnect costs. A design exploration tool for reconfigurable architectures is currently under development at LESTER-UBS. The tool allows various reconfigurable architectures to be compared for different applications and sets of constraints. One of the challenges of the tool is the ability to estimate interconnect costs at a high level of abstraction. This project explores the use of the Adaptive System on a Chip (aSoC) tiled architecture, developed at UMASS as a target architecture for design exploration. aSoC provides an important capability to the LESTER tool by allowing interconnect costs to be modeled very early in the design process by partitioning and placing each portion of the computation into a square tile on a 2D grid. aSoC is primarily an interconnect architecture, based on static scheduling of virtual interconnects onto a highly characterized and regular physical interconnect fabric. aSoC supports a wide variety of cores, including dedicated, hardware programmable and software programmable thus allowing a wide range of design exploration.