• DocumentCode
    1664800
  • Title

    A 1.45GHz 52-to-162GFLOPS/W variable-precision floating-point fused multiply-add unit with certainty tracking in 32nm CMOS

  • Author

    Kaul, Himanshu ; Anders, Mark ; Mathew, Sanu ; Hsu, Steven ; Agarwal, Amit ; Sheikh, Farhana ; Krishnamurthy, Ram ; Borkar, Shekhar

  • Author_Institution
    Intel, Hillsboro, OR, USA
  • fYear
    2012
  • Firstpage
    182
  • Lastpage
    184
  • Abstract
    High-throughput floating-point computations are key building blocks of 3D graphics, signal processing and high-performance computing workloads [1,2]. Higher floating-point precisions offer improved accuracy at the expense of performance and energy efficiency, with variable-precision floating-point circuits providing run-time precision selection [3]. Real-time certainty tracking enables variable-precision circuits not only to operate at the higher energy efficiency of low-precision datapaths, but also to preserve high-precision accuracy. A variable-precision floating-point unit that performs fused multiply-adds (FMA) with single-cycle throughput while supporting operation in either 1-way single-precision (24b mantissa), 2-way 12b precision or 4-way 6b precision modes is fabricated in 32nm High-k/Metal-gate CMOS [4]. Simultaneous floating-point certainty tracking, preshifted addends, a combined rounding and negation incrementer, efficient reuse of mantissa datapath for multiple parallel lower precision calculations, robust ultra-low voltage circuits, and fine-grained clock gating enable nominal energy efficiency of 52GFLOPS/W (IEEE 32b single-precision, measured at 1.45GHz, 1.05V, 25°C) with a dense layout occupying 0.045mm2 (Fig. 10.3.7) while achieving: (i) scalable performance up to 3.6GFLOPS (single-precision), 96mW measured at 1.2V; (ii) up to 4× higher throughput of 14.4GFLOPS with variable-precision, while maintaining single-precision accuracy; (iii) fast single-cycle precision reconfigurability; (iv) precision mode-dependent power consumption for up to 40% clock power reduction; (v) near-threshold single-precision operation measured at 300mV, 1.75MHz, 11μW; and, (vi) peak energy efficiency of 321GFLOPS/W (single-precision) and 1.2TFLOPS/W (6b precision) at 325mV, 25°C.
  • Keywords
    CMOS integrated circuits; energy conservation; floating point arithmetic; 3D graphics; certainty tracking; energy efficiency; fine-grained clock gating; frequency 1.45 GHz; high-k/metal-gate CMOS; high-performance computing workloads; high-throughput floating-point computations; mantissa datapath; run-time precision selection; signal processing; size 32 nm; variable-precision floating-point circuits; variable-precision floating-point fused multiply-add unit; Accuracy; CMOS integrated circuits; Energy efficiency; Energy measurement; Power measurement; Throughput; Voltage measurement;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2012 IEEE International
  • Conference_Location
    San Francisco, CA
  • ISSN
    0193-6530
  • Print_ISBN
    978-1-4673-0376-7
  • Type

    conf

  • DOI
    10.1109/ISSCC.2012.6176987
  • Filename
    6176987