DocumentCode
1664808
Title
Reconfigurable mapping functions for online architectures
Author
Harinath, Shyamnath ; Sass, Ron
Author_Institution
Dept. of Electr. & Comput. Eng., Clemson Univ., SC, USA
fYear
2003
Abstract
Content addressable memory is an expensive component in fixed architecture systems however it may prove to be a valuable tool in online architectures (that is, run-time reconfigurable systems with an online decision algorithm to determine the next reconfiguration). In this paper we define a related problem called an arbitrary mapping function and describe an online architecture. We look at four implementations of an arbitrary mapping function component and compare them in terms of space (number of CLB used), reconfiguration time, and component latency. All of the implementations offer low latency; which is the primary reason to use a content addressable memory or an arbitrary mapping function. Three of the implementations trade large size for very fast reconfiguration while the last implementation is extremely conservative in space but has a large reconfiguration time.
Keywords
content-addressable storage; memory architecture; parallel architectures; reconfigurable architectures; CLB; arbitrary mapping function; component latency; configurable logic blocks; content addressable memory; online architectures; online decision algorithm; reconfigurable mapping functions; reconfiguration time; run-time reconfigurable systems; Associative memory; CADCAM; Computer aided manufacturing; Computer architecture; Delay; Feedback loop; Logic arrays; Logic programming; Parallel architectures; Reconfigurable logic;
fLanguage
English
Publisher
ieee
Conference_Titel
Parallel and Distributed Processing Symposium, 2003. Proceedings. International
ISSN
1530-2075
Print_ISBN
0-7695-1926-1
Type
conf
DOI
10.1109/IPDPS.2003.1213318
Filename
1213318
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