DocumentCode
1664830
Title
Dependability analysis: a new application for run-time reconfiguration
Author
Leveugle, R. ; Antoni, L. ; Fehér, B.
Author_Institution
TIMA Lab., Grenoble, France
fYear
2003
Abstract
The probability of faults, and especially transient faults, occurring in the field is increasing with the evolutions of the CMOS technologies. It becomes therefore crucial to predict the potential consequences of such faults on the applications. Fault injection techniques based on the high level descriptions of the circuits have been proposed for an early dependability analysis. In this paper, a new approach is proposed, based on emulation and run-time reconfiguration. Performance evaluations and practical experiments on a Virtex development board are reported.
Keywords
fault simulation; field programmable gate arrays; hardware description languages; parallel architectures; performance evaluation; reconfigurable architectures; CMOS technologies; Virtex development board; dependability analysis; emulation; performance evaluations; run-time reconfiguration; transient faults; CMOS technology; Circuit faults; Circuit simulation; Emulation; Field programmable gate arrays; Hardware; Information analysis; Prototypes; Runtime; Space technology;
fLanguage
English
Publisher
ieee
Conference_Titel
Parallel and Distributed Processing Symposium, 2003. Proceedings. International
ISSN
1530-2075
Print_ISBN
0-7695-1926-1
Type
conf
DOI
10.1109/IPDPS.2003.1213319
Filename
1213319
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