Title :
A TDC-less ADPLL with 200-to-3200MHz range and 3mW power dissipation for mobile SoC clocking in 22nm CMOS
Author :
August, Nathaniel ; Lee, Hyung-jin ; Vandepas, Martin ; Parker, Rachael
Author_Institution :
Intel, Portland, OR, USA
Abstract :
Mobile SoC designs demand a low-power clocking system to maximize battery life. The host PLL is critical since it must remain enabled to support always-on, always-connected operation. In addition, the host PLL should offer wide frequency range, low area, flexible bandwidth, scalability to future manufacturing processes, negligible lock time compared to the power-state-cycling time, and acceptable period jitter for clocking digital logic.
Keywords :
CMOS integrated circuits; clocks; phase locked loops; system-on-chip; CMOS; TDC-less ADPLL; always-connected operation; always-on operation; battery life maximisation; digital logic; frequency 200 MHz to 3200 MHz; lock time; low power clocking system; mobile SoC clocking; mobile SoC design; period jitter; power 3 mW; power dissipation; power-state-cycling time; size 22 nm; Arrays; Clocks; Jitter; Noise; Phase frequency detector; Phase locked loops; Tuning;
Conference_Titel :
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2012 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4673-0376-7
DOI :
10.1109/ISSCC.2012.6176995
